Job Description

• Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure
• Setup and Synthesizing RTL
• Timing closure through various methods and strategies; preferable in-depth experience in top-level STA
• EM/IR Analysis,
• Place and Route
• Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques
• Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
• Flow and Methodology Development
• Collaborating with IC Design RTL Engineers

• TCL/PERL Scripting
• Proficiency in related EDA Tools
• Full physical design cycle experience: RTL to Tape-out
• Excellent verbal and written communication skills

• Minimum: Bachelor's degree required in Electrical Engineering or Electronics Engineering
• 12+ Years of relevant experience

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